All articles
36 articles
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Optimizing Image Processing with Verilog on FPGA: Techniques and Performance Enhancements
Published in International Journal of VLSI Circuit Design & Technology Read article
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Visualizing Complexity: Navigating Algorithms with Algorithm Visualizer
Abstract: We think that studying algorithms may be amusing and exciting. Many students are currently struggling, but we hope to change that. Our strategy is to emulate gaming while learning. We're building hands-on learning exercises, such as mazes and patterns, to convey key concept. To help students understand how algorithms function in practice, we also use some stunning visualizations. Three major categories of algorithms are under our purview: sorting, pathfinding, CPU …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 1, 2024 · pp. 21–26 Read article
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Innovative CNN Strategies for Superior Handwritten Digit Recognition
Abstract: Handwritten digit recognition is a fundamental problem in the field of computer vision and machine learning with numerous applications, such as postal code recognition, bank check processing, and digitizing historical documents. Convolutional Neural Networks have demonstrated remarkable success in various image recognition tasks, making them a popular choice for digit recognition. In this study, we present an enhanced approach to handwritten digit recognition using CNNs. Handwritten digit recognition plays a …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 1, 2024 · pp. 27–34 Read article
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Bank Locker Security System Using Machine Learning
Abstract: The Bank Locker Security System integrates cutting-edge technology solutions to strengthen the security of bank locker facilities. This system uses biometric identification techniques, such as facial recognition and fingerprint scanning, to confirm users' identities before granting them access to the lockers. Furthermore, access control techniques based on RFID technology are employed to augment security protocols. The locker area is equipped with real-time monitoring and alerting tools that enable fast detection …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 1, 2024 · pp. 16–20 Read article
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Automatic Laser Welding Machine Using PLCs
Abstract: This paper presents the design and implementation of an automatic laser welding machine controlled by a Programmable Logic Controller (PLC) technology. Laser welding has gained significant attention in various industries due to its precision, speed, and efficiency. However, manual operation of laser welding systems can be labor-intensive and prone to errors. The proposed system aims to address these challenges by automating the welding process using PLC-based control. The system architecture …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 1, 2024 · pp. 9–15 Read article
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Smartphone-Controlled IoT Robot for Safety and Automation
Abstract: Robotics Automation is a field that's growing fast. Industrial robots are being used a lot in different parts of the world recently. They are becoming more and more popular because they help make things faster, work well in many situations, and make money. In this project, we want to make a special robot that you can control with your Smartphone. It can do many different tasks and is strong and …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 2, Issue 1, 2024 · pp. 1–8 Read article
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Efficient Gabor Filter Design Using Verilog HDL with Multiplier-accumulator (MAC) Implementation
Abstract: This paper introduces a novel and enhanced Gabor filter design aimed at addressing the demands of image processing applications using the Verilog Hardware Description Language (HDL). Specifically, it leverages the Reconstruct Gabor filter technique to elevate the performance and quality of standard image outputs. The primary objective of this research endeavor is to simplify the study, conduct an in-depth analysis, and substantially enhance the design's efficiency, all while ensuring the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 40–46 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
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Implementation of Adders Using Ternary Based Multiple Valued Logic
Abstract: In today’s world VLSI chips are widely used in various branches of Engineering like Voice and Data communication networks, Digital signal processing, Computers, Commercial Electronics, Automobiles, Medicine and many more. So, there have been major advances in IC technology which have both made feasible and generated great interest in electronic circuits which employ more than two discrete levels of signals such circuits called Multiple valued logic circuits, offer several potential …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 1–8 Read article
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Designing Digital Filters of Underwater Wireless Sensor Node
Abstract: Underwater Wireless Sensor Networks (UWSNs), an emerging area, integrate sensing, computing, and communication into a single compact device. The digital data is acquired using an FPGA (Field Programmable Gate Array), and the fusion of numerous sensor data is accomplished in the sensor node’s ARM (Advanced RISC Machine) CPU. The sensor interfacing circuit should connect the sensor to the sensor node’s data collecting system. The data from these sensors may be …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 43–53 Read article
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WSN with IoT Using Raspberry Pi as a Tool for Communication
Abstract: Wireless systems based on IoT have developed exponentially in various aspects. The Internet of Things (IoT) is a network in which physical devices, sensors, and other objects communicate among themselves without the involvement of humans. The WSN (Wireless sensor network) is a central component of IoT that has escalated into various applications in the real world. Many industries are turning towards industrial automation as it provides increased efficiency, reduced costs, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 34–42 Read article
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article