STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of VLSI Design Tools and Technology

Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit

  1. Devendra Singh Thakur
  2. Sateesh Kourav
  3. Prof. Sunil Kumar Shah
  4. Yashwant Singh Thakur

Abstract

Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The efficiency of an algorithm is determined by its speed, power, and ALU utilization. Field-Programmable Gate Arrays (FPGAs) have developed as adaptable platforms for accelerating a wide range of computational operations. The Floating-Point Arithmetic Logic Unit (FALU) is a fundamental component of current processors that is responsible for performing sophisticated floating-point arithmetic calculations. This review paper digs into the improvements, problems, and design techniques of FPGA-based FALUs. The essay discusses significant architectural approaches, optimization methodologies, and performance assessments, providing insight into the state-of-the-art in FPGA FALU design. Floating-point arithmetic is a fundamental building block of scientific and engineering calculations, allowing for the representation and manipulation of real numbers with a broad range of magnitudes. Because of the parallelism, reconfigurability, and possibility for customized acceleration, FPGA-based FALUs have gained traction as processors demand faster computational speed while preserving energy economy.

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