STM Journals Peer-reviewed research from Consortium e-Learning Network

2 publications

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    Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit

    By Devendra Singh Thakur, Sateesh Kourav, Prof. Sunil Kumar Shah, Yashwant Singh Thakur

    Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …

    Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article

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    Coarse-grained Logic Interface with Floating-point Arithmetic Unit: A Review

    By Devendra Singh Thakur, Sunil Kumar Shah, Sateesh Kourav, Anoop Kumar Dubey, Yashwant Singh

    Abstract: One of the key elements of their design, which has a substantial impact, is their choice of programmable connectivity and logic capabilities. The FPGA architecture has a significant impact on the speed performance, space efficiency, and power consumption of the finished device. This examination examines the evolution of programmable logic devices over time, the underlying programming paradigms that underpin programmability, and the most important findings from architectural system research. We …

    Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 11, Issue 2, 2023 · pp. 18–24 Read article

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