STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microelectronics and Solid State Devices

Low-Complexity VLSI Hardware Design for DWPT

  1. Vikas Tiwari
  2. B. K. Mohanty

Abstract

AbstractThis paper presents a low-complex discrete wavelet packet transform (DWPT) architecture design for power constrained and cost sensitive healthcare applications. The multiplier-adder unit of the proposed multiplier-based designs of DWPT is replaced by the shift-add unit to reduce the area complexity of parallel structure. The proposed low-complexity multiplier-less design could be used an alternative to the existing multiplier-based design for hardware efficient realization of multi-level DWPT.Keywords: DWPT, Hardware complexity, VLSI, multiple constant multiplicationCite this ArticleVikas Tiwari, B.K. Mohanty. Low-Complexity VLSI Hardware Design for DWPT. Journal of Microelectronics and Solid State Devices. 2017; 4(3): 28–32p.
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