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Low-Complexity VLSI Hardware Design for DWPTBy Vikas Tiwari, B. K. Mohanty
Abstract: AbstractThis paper presents a low-complex discrete wavelet packet transform (DWPT) architecture design for power constrained and cost sensitive healthcare applications. The multiplier-adder unit of the proposed multiplier-based designs of DWPT is replaced by the shift-add unit to reduce the area complexity of parallel structure. The proposed low-complexity multiplier-less design could be used an alternative to the existing multiplier-based design for hardware efficient realization of multi-level DWPT.Keywords: DWPT, Hardware complexity, VLSI, …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 28–32 Read article →