Journal of Microelectronics and Solid State Devices
Volume 4, Issue 3 (2017)
Published
Table of contents
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Modeling and Simulation of Pentacene based Organic Thin Film Transistors with Organic Gate Dielectrics
Abstract: AbstractTwo structures of pentacene organic thin film transistors (OTFT) with organic dielectrics, polymethyl methacrylate (PMMA) and polyvinyl alcohol (PVA) have been numerically simulated with TCAD ATLAS tool. Output and transfer characteristics were simulated and mobility, threshold voltage, sub threshold swing (SS) and current on/off ratio that play a part in the increment of conductivity of device were extracted. The authors show that the semiconductor-insulator interface actively affects the performance of …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 13–18 Read article
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Performance Analysis of 1-Bit Half Adder using Different Combinational MOS Logics
Abstract: AbstractAdder is required for many processors designing like microprocessors, digital signal processors, image processing and various VLSI applications. The overall performance of system depends upon the adder circuits due to its presence mainly in critical paths of system. This paper presents half adder circuits using different combinational MOS logics. All the circuits were analyzed to find the most suitable circuit which consumes less power without costing the speed of the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 19–27 Read article
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Low-Complexity VLSI Hardware Design for DWPT
Abstract: AbstractThis paper presents a low-complex discrete wavelet packet transform (DWPT) architecture design for power constrained and cost sensitive healthcare applications. The multiplier-adder unit of the proposed multiplier-based designs of DWPT is replaced by the shift-add unit to reduce the area complexity of parallel structure. The proposed low-complexity multiplier-less design could be used an alternative to the existing multiplier-based design for hardware efficient realization of multi-level DWPT.Keywords: DWPT, Hardware complexity, VLSI, …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 28–32 Read article
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Effect of Aluminium Nitride Layer on the Electrical Performance of Microelectronic HEMTs
Abstract: AbstractIn this simulation work, a series of simulation outputs are reported related to the AlGaN/GaN single-heterojunction high electron mobility transistors (HEMTs). The effect of aluminium nitride nucleation layer on the drain characteristics is significant in single-heterojunction AlGaN/GaN HEMTs. The effects of drain voltage and gate voltage on the drain current are studied in the designed and simulated device structures. This simulation work may be a useful prediction to fabricate the …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 9–12 Read article