STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Electronic Design Technology

Optimization of a Digital Adder Design Using MOSFET and FinFET Technology

  1. Ritu Dagar
  2. Preet Kaur

Abstract

AbstractIn this study, a very low power high speed Adder is presented by using short gate mode technique and voltage scaling system for FinFET. MOSFET and FinFET technique is used on 32 nm by adders which compare delay and average power. Parametric study of fins vs. power is also performed in the study. Synopsys HSPICE software is used for obtaining the simulation results. Simulation results show that low power is obtained in short gate mode Adder technique. When FinFET is applied in the Adder, delay is also improved.Keywords: 32 nm, FinFET, adder, MOSFET, CMOSCite this ArticleRitu Dagar, Preet Kaur. Optimization of a Digital Adder Design Using MOSFET and FinFET Technology. Journal of Electronic Design Technology. 2018; 9(2): 30–33p.
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