Rosalin Pradhan
- Affiliation
- Department of Electrical Engineering, Indira Gandhi Institute of Technology, Sarang, Dhenkanal
- Department
- Assistant Professor
- Location
- India
Rosalin Pradhan
4 articles
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Deep Learning-Based Thermal Prediction Models for Solid-State Electronic Devices
Abstract: The rapid advancement of solid-state electronic devices in high-performance computing, communication systems, automotive electronics, and renewable energy applications has significantly increased concerns related to thermal management and device reliability. Excessive heat generation in semiconductor devices adversely affects operational efficiency, switching performance, lifespan, and overall system stability. Traditional thermal prediction methods often require complex numerical computations and extensive simulation time, making them less suitable for real-time monitoring and adaptive control applications. …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Photonic-Assisted Spintronic Solid-State Switching Model for High-Speed Memory Devices
Abstract: The rapid advancement of high-speed computing and data-centric applications has intensified the demand for energy-efficient and ultra-fast memory technologies. This paper proposes a Photonic-Assisted Spintronic Solid-State Switching Model for next-generation high-speed memory devices. The proposed framework integrates photonic excitation mechanisms with spintronic switching dynamics to enhance data transfer speed, minimize switching delay, and reduce power dissipation in solid-state memory architectures. By combining optical pulse-assisted spin polarization with magnetic tunnel junction-based …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design
Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article