Bit-interleaving

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• Published Subscription 28 Sep 2023

  Design and Implementation of Low Power and High Speed 10T SRAM with High SNM

  By Anusha Achhina, K Joseph Thanusha, Deepya Yennamaneni

  Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …

  Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article →

• Published Subscription 13 Sep 2023

  A Reliable Low Standby Power 6T SRAM Cell

  By K Joseph Thanusha, Anusha Achhina, Dedeepya Padakanti

  Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …

  Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article →