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4 articles for “Bit-interleaving”
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Design and Implementation of Low Power and High Speed 10T SRAM with High SNM
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell utilizes a strong cross-coupled structure that combines a standard inverter with a stacked transistor and a Schmitt-trigger inverter with a double-length pull-up transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 1, 2023 · pp. 40–65 Read article
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A Reliable Low Standby Power 6T SRAM Cell
Abstract: The project introduces a low standby power 10T (LP10T) SRAM cell that focuses on achieving high read stability and write-ability while minimizing power consumption. The LP10T SRAM cell uses a robust cross-coupled design that combines a Schmitt-trigger inverter with a double-length pull-up transistor and a regular inverter with a stacking transistor. One of the key advantages of the LP10T SRAM cell is that it separates the read path from the …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 33–59 Read article
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Comparison of Bit Error Rate and Interleaver in Coding Scheme
Abstract: The powerful channel coding schemes, namely, those based on turbo codes with different type of interleaver design and iterative scheme of decoding. The Shannon’s predictions to optimal codes would imply random like codes and intuitively implying that the decoding operation on these codes would be prohibitively complex in nature. A brief comparison of Turbo codes with different type interleaver will be given in this section, both in term of actual …
Published in Journal of Mechatronics and Automation · Vol. 7, Issue 1, 2020 · pp. 1–5 Read article
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Schmitt-Trigger Based 12T SRAM Cell with Enhanced Stability
Abstract: In this work, we present a single-ended Schmitt-trigger (ST) based 12T static random access memory (SRAM) cell. The proposed cell employs cross-point data aware write structure, and thus supports bit interleaving architecture to mitigate soft errors. The proposed cell does not suffer from read disturbance as bit line is completely isolated from bit storage node. Simulation is done on 180 nm CMOS technology on Cadence. Read static noise margin (RSNM) …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 5–10 Read article