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4 articles for “short channel effects (SCEs)”
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A Technological Review on Quantum Ballistic Transport Model Based Silicon Nanowire Field Effect Transistors for Circuit Simulation and Design
Abstract: Nanowire MOSFETs are recognized as one of the most promising candidates to extend Moore’s law into nanoelectronics era. This paper reviews the process, application, device physics and compact modeling of Gate All around (GAA) nanowire MOSFETs. The most widely used methods of nanowire synthesis have been discussed. The paper presents the various device optimization techniques and scaling potential of nanowire transistors. A process sensitivity study of silicon nanowire transistors at …
Published in Journal of Nanoscience, NanoEngineering & Applications · Vol. 5, Issue 2, 2015 · pp. 20–31 Read article
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A Two-Dimensional (2D) Analytical Model for Channel Potential and Threshold Voltage of Short Channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET
Abstract: In the present paper, an analytical model for the channel potential of short channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET has been presented using parabolic approximation method. Further, the threshold voltage of the device has been calculated using minimum mid channel potential and the result obtained has been compared with the threshold voltage of Triple Material double gate (TMDG) MOSFET in order to show the improvement in the threshold …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 13–25 Read article
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Comparative Analysis of FD-DMDG SON MOSFET over FD DMDG SOI MOSFET
Abstract: AbstractIn the recent past, Silicon-on-Insulator (SOI) shows better device performance in comparison to bulk Silicon devices but it still suffers from different short channel effects (SCEs). Recently a structure, Silicon on Nothing (SON), has been suggested and investigated. It is structured to be capable of substantial reduction of SCEs and present better electrical characteristics in comparison to SOI. The absence of the buried layer results in the reduced electrostatic coupling …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 9–16 Read article
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Simulation Study of Tapered Shape FinFET
Abstract: During recent years, nonplaner tri-gate (TG) field-effect transistors (FETs) such as FinFETs have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects (SCEs) in the sub50 nm regime. As the device scaled, it is observed that the shape of the rectangular FinFET becomes tapered shape. This paper presents the design and analysis of a tapered-shaped FinFET. By varying the sidewall inclination angle of a rectangular …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 21–31 Read article