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4 articles for “electrostatic scaling”
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Simulation Study of Tapered Shape FinFET
Abstract: During recent years, nonplaner tri-gate (TG) field-effect transistors (FETs) such as FinFETs have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects (SCEs) in the sub50 nm regime. As the device scaled, it is observed that the shape of the rectangular FinFET becomes tapered shape. This paper presents the design and analysis of a tapered-shaped FinFET. By varying the sidewall inclination angle of a rectangular …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 21–31 Read article
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Biopolymer-Based Flocculation for Microplastic Removal: Fenugreek and Okra as Sustainable Alternatives to Synthetic Flocculants
Abstract: Microplastic pollution has emerged as a persistent global environmental concern due to its widespread presence in aquatic ecosystems and potential implications for food chains and human health. Conventional removal approaches, particularly the use of synthetic flocculants such as polyacrylamide (PAM), have demonstrated high removal efficiencies in water treatment applications. However, their use is often associated with environmental concerns including toxicity, non-biodegradable residues, and energy-intensive production processes. In this context, the …
Published in Journal of Polymer & Composites · Vol. 14, Issue 2, 2026 · pp. 1119–1128 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article