Search
5 articles for “cache memory”
-
Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
Abstract: This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 1–13 Read article
-
Application of B-trees for Design of Optimal Page Replacement Technique in Modern Operating Systems
Abstract: Algorithms related to replacing the memory pages in operating systems are critical components of modern operating systems that manage virtual memory efficiently. Current algorithms such as LRU (Least Recently Used), Clock algorithms as well as FIFO (First-In-First-Out), often struggle with the increasing demands of contemporary applications and larger memory hierarchies. This research work proposes a novel approach utilizing B-tree data structures to design an optimal page replacement technique. The proposed …
Published in International Journal of Data Structure Studies · Vol. 3, Issue 2, 2025 · pp. 23–30 Read article
-
Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
-
Traversal Speed Comparison of BFS and DFS in Balanced and Skewed Binary Trees
Abstract: In this paper, we provide an analysis of how well both breadth-first search (BFS) and depth-first search (DFS) algorithms perform while wandering through two kinds of binary trees: balanced and skewed. The research was motivated by the practical application of storing files and directories in a certain type of parent-child relationship through the use of hierarchical file systems (e.g., windows explorer). The result of measuring how fast and versatilely these …
Published in International Journal of Data Structure Studies · Vol. 4, Issue 2, 2026 Read article
-
An Investigative Study on Cache-Oblivious Data Structures
Abstract: Cache-oblivious data structures and data management systems have emerged as critical components in modern computing environments, aiming to optimize memory access patterns across different levels of the memory hierarchy without explicit knowledge of cache sizes or configurations. This study presents an overview of cache-oblivious techniques, including adaptive data structures, compression, parallel processing, and security considerations. The workexplores future directions in cache-oblivious systems, such as non-volatile memory support, graph processing, edge …
Published in International Journal of Data Structure Studies · Vol. 1, Issue 2, 2023 · pp. 33–37 Read article