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2 articles for “binary multiplier”
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Power and Area - Aware Recursive Multiplier Architecture Utilizing Polymer Composites for Neural Network Acceleration
Abstract: Approximate computing is widely applied in error - tolerant systems as an effective technique to enhance circuit performance by deliberately allowing occasional inaccuracies instead of strictly ensuring precise results for every computation. Among the fundamental building blocks of digital systems, multipliers play a crucial role in signal processing, control systems, and machine learning applications; however, they demand significant power, silicon area, and timing resources. Leveraging error - tolerant approximate multipliers …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1320–1337 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article