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2 articles for “Urdhva Tiryagbhyam”

• Published Subscription Review Article 5 May 2026

  64 Bit ALU DESIGN USING VEDIC MATHEMATHICS

  By Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar

  Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 2 Apr 2026

  Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics

  By K. Durga Devi, B. Hema Shankar, A. Phani Kumar, J. Vivek, Dr. T. Saran Kumar, Dr. Akula Pravin

  Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …

  Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article →