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2 articles for “Ultra Low Power (ULP)”
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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article