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7 articles for “Phase Frequency Detector”
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Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
Abstract: This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 18–28 Read article
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Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article
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Design of Digital Frequency Sensitive Phase Detector and study its Phase Response
Abstract: In this paper, a digital frequency sensitive phase detector (PD) with voltage controlled phase response is presented. This scheme is based on classical type flip-flop phase detectors and an improved PD operating on both edges of the input sequence. Phase-to-voltage response characteristic control is accomplished by the additional feedback of the low-pass filter output voltage to reset the control pin input. In this paper, we have presented a simulated frequency …
Published in Journal of Microwave Engineering and Technologies · Vol. 8, Issue 3, 2021 · pp. 43–51 Read article
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Characterization of Low Power-Low Jitter Digital PLL
Abstract: The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 23–32 Read article
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All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey
Abstract: An all-digital phase locked loop (ADPLL) plays a great role in decreasing the development time of an application-specified integrated circuit (ASIC) products and helps to meet the time-to market requirement of product, because an ADPLL can be used as an IP core, so it is easily reusable in any design. Now a days ADPLL is being widely used in various fields such as control systems and digital communication systems. This …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 12–17 Read article
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Adaptive-Hysteresis Current Controller Based Shunt Active Power Line Conditioners for Power Quality Improvements
Abstract: This paper presents three-phase shunt active power line conditioners (APLC) for harmonics and reactive powercompensation due to non-linear loads in the distribution network. The compensation process proposed is asinusoidal extraction control method, which consists of positive-sequence voltage detector for regulating thesupply voltage and instantaneous reactive power (p-q) theory for fundamental extraction from the distorted linecurrent. The shunt active filter voltage source inverter’s switching pulses are generated through an adaptivehysteresiscurrent controller …
Published in Journal of Power Electronics and Power Systems · Vol. 1, Issue 1-2-3, 2011 · pp. 1–13 Read article
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Low Power RF QPSK MODEM Design
Abstract: System-level simulation including design of CMOS circuits for radio frequency QPSK MODEM targeting applications in 2.45 GHz industrial, scientific and medical (ISM) band has been presented in this paper. Based on the QPSK architecture, the MODEM consists of an analog mixer using a voltage multiplier, a 90 °phase shifter, delay circuits, a voltage adder and a filter to detect the information. A code reuse subsystem block consisting of Chebyshev filter …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 75–86 Read article