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4 articles for “Modular arithmetic”
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Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Abstract: The three operands binary adder is a basic function used in the creation of modular arithmetic in various algorithms, such as the pseudorandom bit generator and cryptography. The CS3A carry save adder is commonly used to perform this operation. Nevertheless, the operation's outcome delayed the transmission of O(n) because of the ripple carry step. A dual-optoic adder for parallel prefix computation, such as the Han-Carlson method, can be used to …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 14–22 Read article
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Design and Implementation of 256-bit Vedic Multiplier on Reconfigurable Platform
Abstract: Multiplication is a fundamental arithmetic operation in digital signal processing and embedded systems. Traditional multiplier architectures often suffer from increased latency and resource utilization when scaled to higher bit widths. Vedic Mathematics, an ancient Indian technique, offers a novel and efficient alternative. This paper presents the design and implementation of a 256-bit Vedic multiplier using the Urdhva Tiryakbhyam Sutra on a reconfigurable hardware platform, specifically FPGA. The proposed architecture decomposes …
Published in Journal of Materials & Metallurgical Engineering · Vol. 15, Issue 3, 2025 · pp. 56–65 Read article
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An Automated Smart Contract Repair Framework for Reentrancy, Integer Overflow, and Denial- of-Service Vulnerabilities
Abstract: This paper introduces a novel static analysis framework designed to bridge a long-standing gap in Ethereum smart contract security: the disconnect between vulnerability detection and automated remediation. Although widely adopted tools such as Slither and Oyente are highly effective at identifying security weaknesses, they stop short of providing actionable fixes. As a result, developers manually patch vulnerabilities, a process that is not only time-consuming but also susceptible to human error …
Published in Journal of Computer Technology & Applications · Vol. 17, Issue 1, 2026 · pp. 31–41 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article