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4 articles for “HVL”
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Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT
Abstract: Verification of a design is as important as the design itself to make it work in a practical scenario. Verification phase is an important phase in System on Chip (SoC) design cycle and used to take 70% to 80% of the total design time. A verification environment may be prepared simply using a Hardware Verification Language (HVL) only without using any methodology or using a HVL with verification methodology. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 114–121 Read article
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Influence of Bi2O3 on Physical, Optical and gamma radiation Properties of BaO-Bi2O3-B2O3-CuO and BaO-Bi2O3-B2O3-Fe2O3 glasses
Abstract: In this present work glasses with chemical composition 30BaO-XBi2O3-(69-X)B2O3-1CuO and 30BaO-XBi2O3-(69-X)B2O3-1Fe2O3 (X = 0, 5, 10, 15, 20 and 25 mole%) have been prepared and labeled as BBBC and BBBF series, respectively. Traditional quenching method was employed for making these samples. XRD diffractograms confirmed that the materials were amorphous. Physical, optical and structural properties were studied with the influence of Bi2O3 concentration. The density of both BBBC and BBBF series …
Published in Journal of Polymer & Composites · Vol. 10, Issue 1, 2022 · pp. 20–31 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article