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3 articles for “HSPICE”
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Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Design And Implementation of Anti-Interference Low Power Double-Edge Trigger Flip-Flop Based On C-Element
Abstract: Double-Edge Triggered Flip-Flops (DETFFs) will use a lot more power when there are glitches and interference in the signal input. This work proposes an anti-interference low-power DETFF based on C-elements to efficiently lower the power consumption. This DETFF employs an enhanced C-element, which successfully filters input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge frequencies. To lower its latency, the C-element has additionally …
Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 36–44 Read article