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4 articles for “4-bit CPU”
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Design and Implementation of a 4-Bit Breadboard CPU Using Digital Integrated Circuits
Abstract: This paper presents the design and hardware realization of a simple 4-bit CPU built using discrete TTL integrated circuits on a breadboard. The CPU employs a 4-bit common data bus with tri-state buffers for device arbitration, three 4-bit registers (Register A, Register B, and an Output Register) implemented with 74LS175 quad D flip-flops, and a 4-bit ALU for addition/subtraction using a 74LS83 adder and XOR gates. Manual control signals (load, …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 Read article
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A Reviewed Study On Cpu-Optimized Parameter-Efficient Fine- Tuning For Large Language Models To Increase Accuracy Using Lora
Abstract: The fast proliferation of Large Language Models (LLMs) has increased the need to optimize the process of fine-tuning but the existing workflows that require a GPU are still expensive, intensive, and unavailable to most researchers. This paper is driven by the desire to have a more cost-efficient and democratized version by examining a CPU-efficient implementation of Parameter-Efficient Fine-Tuning (PEFT) based on Low-Rank Adaptation (LoRA). The major purpose of the study …
Published in Recent Trends in Parallel Computing · Vol. 13, Issue 1, 2026 Read article
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Card Fraud Detection Using Artificial Neural Network and Multilayer Perception Algorithm
Abstract: Fraud has posed a significant challenge for merchants, especially in the online business sector, over the course of many years. This is primarily due to the advancements in technology that have made credit card transactions a common method of payment. Credit card fraud refers to the unauthorized use of a credit card by an individual for personal purposes, without the owner's consent and with no intention of paying for the …
Published in International Journal of Algorithms Design and Analysis Review · Vol. 1, Issue 1, 2023 · pp. 21–30 Read article
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Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article