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193 articles for “transistor”
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
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A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
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Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
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A Low Power Variable Gain Amplifier for Biomedical Application
Abstract: This paper describes the design and simulation of low power variable gain amplifier used for biomedical application like hearing aid, Electronic Cardiograph and neural recording system. The MOS transistor is designed to operate in subthreshold region for low power application. The gain of amplifier is changed by selecting different values of input capacitor in the frequency range of 20 Hz–20 KHz. The simulated total power dissipation is 3µW. The gain …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 7–12 Read article
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High-speed CMOS ADCs Design
Abstract: This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 59–74 Read article
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Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era
Abstract: The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate. Keywords: Silicon on insulator (SOI), short channel effect (SCE) [2], buried oxide (BOX)
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 52–58 Read article
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Simulation Study of Tapered Shape FinFET
Abstract: During recent years, nonplaner tri-gate (TG) field-effect transistors (FETs) such as FinFETs have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects (SCEs) in the sub50 nm regime. As the device scaled, it is observed that the shape of the rectangular FinFET becomes tapered shape. This paper presents the design and analysis of a tapered-shaped FinFET. By varying the sidewall inclination angle of a rectangular …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 21–31 Read article
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Switched Capacitor-based RC Filter
Abstract: Today we know that the demand of low voltage for low power integrated circuits (ICs) are used for growing the portable equipment in all the markets including telecommunication, computers and customer electronics with smaller size. The low voltage need for ICs is also motivated by the new dip submicron complementary metal oxide semiconductor (CMOS) technology scaling that required all transistors of smaller size. In current years, a lot of researches …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 32–40 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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Layout Design, Fabrication and Characterization of n-Channel MOSFET
Abstract: Primary force behind evolution of semiconductor industry is MOSFET, after its first IC based experimental demonstration in 1960s. It is fundamental working unit of most of the electronic circuits like cells in living being. Number of devices on a single chip has been increased with rapid phase with evolution of new technology of materials. Today there are more than 4 billion transistors are there on a single chip with effective …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 13–18 Read article
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Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Abstract: Nanowires are inimitable materials for considering phenomenon in nanoscale regime. Nanowires development exhibits ample of applications by controlling their, structure, composition as well as their electrical properties. This paper review diverse types of nanowires, nanowire field-effect transistor (NWFET) structure and their comparison with novel devices. Firstly, this paper describes different types of nanowires and nanowire heterostructure that shows nanowire heterostructures eliminates various factors that limit the performance of homogeneous nanowire …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 19–32 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique
Abstract: In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 45–55 Read article