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190 articles for “VLS”
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A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique
Abstract: In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 45–55 Read article
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A Novel Approach Based On-Chip High Speed Optical Interconnection Network
Abstract: On-chip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication problem and obtain high-performance integrated circuits. On-chip interconnects are an important performance limiting factor in present day VLSI design. Performance optimization has always been a critical step in the designing of integrated circuits. In this paper, an optical interconnect in 1550 nm range is being implemented using opti-system software. A novel approach is …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 41–48 Read article
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Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization
Abstract: Multipliers play important role in the digital VLSI design. Computational Speed, power consumption, and area are the major parameters on which the performance of the device depends. In digital design, there are different multiplication methods or algorithms. Each algorithm is having its own advantage and disadvantage. In this paper, implementation of five different types of 8-bit multipliers namely Array multiplier, Booth multiplier, Truncated multiplier, Pipelined multiplier, and Vedic multiplier has …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 22–34 Read article
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Design and Validation of Low Power High Speed area effective comparator using CMOS Technology
Abstract: The most fundamental arithmetic comparisons in a digital comparator involve comparing two numbers that are greater than, less than, or equal to each other. While doing enormous level arithmetic comparisons, a digital comparator needs more space, which results in higher power consumption and a delayed response. This can be solved by using N-bit comparator with two modules using 45GPDK CMOS Technology. An N-bit comparator can operate at extremely high speeds …
Published in Recent Trends in Electronics Communication Systems · Vol. 10, Issue 2, 2023 · pp. 20–29 Read article
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A Review of Experimental and Numerical Investigation on the Heat Transfer in Micro-Channel Heat Exchanger for Various Nano Fluids
Abstract: AbstractA tremendous amount of work has been carried out on micro and nanoscale heat exchanger. Cooling requirement is increasing day by day in field of, high performance Aircraft gas turbine engines, Heat pumps, Air conditioning, Heat recovery ventilators, Integrated circuits (IC), VLSI devices, Computer chips, Printed circuit boards and biomedical applications etc. Many investigators focused on parameters such as Reynolds number, cross cut length, pressure drop, particle concentration of Nano …
Published in Recent Trends in Fluid Mechanics · Vol. 5, Issue 3, 2018 · pp. 1–7 Read article
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Evaluation of OTA Amplifier Using EEG Signals
Abstract: AbstractOver the last few years, there has been a tremendous exploration in VLSI industries in response to scaling trends towards deep submicron technology. Demand for low power and efficient amplification are rising in day-to-day life. In the process of scaling the CMOS nanometer demand low supply, which is helped to design digital circuit realization at very low power consumption. But it is not valid for analog circuit realization. The related …
Published in Trends in Opto-electro & Optical Communication · Vol. 10, Issue 2, 2020 · pp. 5–14 Read article
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Low-power, High-speed, Full-swing Hybrid Full Adder
Abstract: Abstract: Nowadays VLSI design demands low area and low-power consumption. In this study, a low-power, high-speed, full-swing 1-bit hybrid full adder is proposed. The hybrid full adder is decomposed into three sub-modules. For each sub-module, designs are different. Module 1 and 2 are designed using pass transistor logic (PTL) and Module 3 uses transmission gates to produce carry signal. Then by proposed low-power, high-speed hybrid full adder circuits play a …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 7, Issue 3, 2019 · pp. 22–29 Read article
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Designing and Analysis of a Negative Bias Temperature Instability Sensing Circuit
Abstract: Scale down the size of devices introduce the effect of negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) in very-large-scale integration (VLSI) chip design and the major concern is to minimize these effects to a nominal value. In the paper, authors focus in minimization of NBTI effect and develop a noble degradation monitoring sensor circuit named SCHIMOS. A comparison is stated between an …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 8, Issue 1, 2020 · pp. 6–11 Read article
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Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools
Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article
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Optimal Cell Sizing of CMOS Two-Stage Operational Amplifier using Cuckoo Search Algorithm
Abstract: Abstract: Operational amplifier (op-amp) is commonly used in different analog circuits such as amplifiers, oscillators, comparators, digital to analog converters, analog to digital converters, mixers etc. Manual cell sizing of a CMOS based op-amp circuit for VLSI application is a challenging, boring, and time-consuming work for engineers. So that, the automatic cell sizing of an op-amp is an eminent topic of growing technical and cost-effective significance. An evolutionary algorithm (EA) …
Published in Journal of Artificial Intelligence Research & Advances · Vol. 6, Issue 2, 2019 · pp. 109–118 Read article
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Low power high performance CMOS Schmitt Trigger using nanoscale CMOS Technology
Abstract: This paper presents different low voltage adjustable CMOS Schmitt trigger at 90nm technology. This paper proposes the transient response and noise response analysis of CMOS Schmitt trigger circuit which will give noisy input signals with less noise response and also applicable for low power. It enumerates reduction of power consumption, which is in major demand in the field of VLSI. The CMOS device is used to achieve better power consumption, …
Published in Journal of Mobile Computing, Communications & Mobile Networks · Vol. 5, Issue 1, 2018 · pp. 28–35 Read article
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FPGA Implementation of Cryptographic Algorithm for Internet of Things (IoT)
Abstract: Internet of Things (IoT) is an advanced version of internet where it is not just the mobile phones and computers that is connected to internet but also the other electronic objects that get connected to it. IoT describes a system where items in the physical world, and sensors within or attached to these items, are connected to the internet via wireless and wired internet connections. These sensors can use various …
Published in Journal of Web Engineering & Technology · Vol. 3, Issue 2, 2016 · pp. 28–34 Read article
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Review of TDC-based on Vernier Ring Oscillator Time to Digital Converter
Abstract: Abstract: The objective of this paper is to review the state-of-the-art of Vernier TDC techniques to achieve high resolution. Modern VLSI technology is mainly driven by digital circuits because a digital circuit has many advantages over analog circuits. To achieving the high-resolution in time-to-digital converter (TDC) is one of the crucial points, it is becoming more suitable for many time-of-flight (TOF) applications because it measures the time difference between two …
Published in Journal of Operating Systems Development & Trends · Vol. 6, Issue 3, 2019 · pp. 30–35 Read article
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Design and Implementation of SRFFT Algorithm Using Floating Point Arithmetic
Abstract: In this world, because of advancing in technology, there is a growing need for people to communicate with each other without delay. Speed is very important in all aspects. It can be improved by reducing arithmetic complexity. At the same time accuracy is also very important. In general, FFT/IFFT is used as a modulation/demodulation kernel in the OFDMsystem. Several techniques are introduced for FFT/IFFT like radix 2 FFT, radix 4 …
Published in Recent Trends in Parallel Computing · Vol. 3, Issue 2, 2016 · pp. 1–8 Read article
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Parallel Computers and Memory Architecture
Abstract: AbstractThe real topic behind this paper is about the parallel PCs and the memory design utilized as a part of this procedure. In this paper, you will be illuminated by review of parallel PCs and different memory designs. Different designs of memory are wonderfully outlined with help of cases and graphs. Each kind of memory is clarified and their favourable circumstances and weaknesses. Keywords: Very Large Scale Integration (VLSI), Symmetric …
Published in Recent Trends in Parallel Computing · Vol. 4, Issue 1, 2017 · pp. 1–3 Read article
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Fabrication and Characterization of Copper Nanowires: An Overview
Abstract: Copper (Cu) is one of the most important metals in modern electronic technology. Keeping in view its role in nanoelectronics, we have fabricated copper nanowires of diameters 100 and 200 nm using Anodic Alumina and polymer membranes as templates. Template-based growth of copper nanowires has been realized using conventional electro deposition technique in an electrochemical cell designed in our laboratory. Fabrication of copper nanowires is one of the most important …
Published in Journal of Nanoscience, NanoEngineering & Applications · Vol. 1, Issue 1, 2011 · pp. 1–16 Read article
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A Real Time Authentication Framework Using Multi-Model Biometrics
Abstract: Online signature as well as finger print verification system is one of the most reliable, fast and cost effective tool for the user authentication. This work examines the implementation of the embedded system for the online signature as well as finger print verification based on field programmable gate arrays. The work describes the complete biometric algorithm for signature and finger print verification based on three stages. Both the inputs are …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 80–86 Read article
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Development of High Impedance Current Mirror Circuit With Its Implementation Using 0.18 μm Technology
Abstract: In this paper, “Development of High Impedance Current Mirror, based super wilson current mirror with both low input and output voltage requirements, along with high output impedance with no any extra biasing circuitry” is implemented. The implemented current mirror uses MOS current dividers to sample the output current to attain very high impedance with a large output and voltage range. A feedback action is used to force the input and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 87–96 Read article
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FPGA Implementation of Binary Integer Decimal based Floating Point Multiplier
Abstract: This paper presents the hardware design of an IEEE P754-2008 complaint multiplier which works on binary integer decimal (BID) encoded decimal floating point numbers. This design uses a single binary multiplier with carry save feedback for both significant multiplication and rounding. It further uses the Dadda or Wallace tree structure to accumulate the partial products. In this design carry select adders, carry look ahead adders and ripple carry adders are …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 97–103 Read article
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Implementation of Register Access Methods for Device Configuration Using UVM
Abstract: Verification of hardware registers conjointly with their monitoring forms a huge part of any verification project. Verification using universal verification methodology (UVM) register layer enables reusability, which consequently eliminates the dependency of register layer on protocol thereby saving time by evading efforts of rewriting register sequences once the protocol changes. This paper constructs the advanced high performance bus (AHB) register verification environment to ease design configuration, thereby promoting reusability and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 132–138 Read article