Search results for “VLS”

Published Subscription 20 Jul 2018

Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime

By Tarun Kumar Sachdeva, S. K. Agarwal, Alok K. Kushwaha

Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article

Published Subscription 28 Aug 2018

A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault

By Ram Vishnu S, Yasodha T

Abstract: Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 72–78 Read article

Published Subscription 26 Dec 2018

A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions

By Pratiksha Kharat

Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article

Published Subscription 3 Dec 2018

Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter

By Jalaja S., Vijaya Prakash A. M

Abstract: Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 1–9 Read article

Published Subscription 3 Dec 2018

Design, Verification and Circuit Level Implementation of a Ballistic MOSFET

By Arun Kumar Chatterjee, B. Prasad

Abstract: A drain current expression is obtained for a nanoscale ballistic MOSFET within the framework of Landauer-Buttiker formalism considering intrinsic silicon channel at low temperature. The model drain current is compared with the numerical simulations of near ballistic nanoMOSFET structure. There is a reasonable agreement between the model and the numerical simulation results. This demonstrates the remarkably low value of the subthreshold slope of ballistic nanoMOSFET. Further, the design structure is …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 15–22 Read article

Published Subscription 3 Dec 2018

An Area Delay Optimized Carry-Select Adder

By Sareeka Tulshiram Deore

Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article

Published Subscription 26 Dec 2018

Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier

By Athira A D, Anjaly Krishnan

Abstract: Multiplication and accumulation are the basic operations which are important in several microprocessors and digital signal processing (DSP) applications to execute dedicated algorithms. Developing high speed MAC is essential for real time DSP application. The MAC unit determines the speed of the overall system and it lies in the critical path. As the demand for high speed design is continuously increasing, the studies related to the field of multipliers and …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 28–35 Read article

Published Subscription 3 Dec 2018

Performance Analysis of CMOS and FinFET Based SRAM

By Jeny Elsa Joji, Sreekala K. S., Dhanusha P. B.

Abstract: As CMOS devices are scaled to nanometer regime, the consequences such as short channel effects and variations in the process parameters are increased which affects the reliability and performance of the circuit. In order to over these issues, FinFET can be used as a suitable replacement for CMOS as it is a promising and better technology without sacrificing the reliability and performance of the applications and the circuit design. In …

Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 23–27 Read article

Published Subscription 20 Apr 2019

Reusable FM0/Manchester Encoding Using QCA

By Harshada Dayanand Malage, Usha Jadhav

Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …

Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article

Published Subscription 16 Jul 2019

Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology

By Lalita Machhindra Landge, Usha Jadhav

Abstract: Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The …

Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 13–22 Read article

Published Subscription 20 Apr 2019

Near Field Wireless Powering of Implantable Devices

By SIMI P THOMAS, Aparna Jose

Abstract: A new WPT system for biomedical applications has been investigated in this paper. First, an implantable receiving antenna with enhanced gain is studied. Then, a transmitting antenna array which can maximize the PTE of the WPT system is designed together with the receiving antenna and head model. Under the transmission distance of 150 mm, the PTE of the designed WPT system reaches a maximum value of 0.28% at the center …

Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 44–50 Read article

Published Subscription 20 Apr 2019

Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications

By Rupali Ashok Walunj, Sachin Dattatraya Pable, Gajanan Kashiram Kharate

Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …

Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article

Published Subscription 1 Mar 2019

Implementation and Analysis of 32-bit pipelined RISC Processor Architecture

By P. Indira, M. Kamaraju

Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …

Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article