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1361 articles for “lay-up”
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Short Review on Lubrication Coatings and Reduction in Friction
Abstract: Specialized Epoxy coatings with a low coefficient of friction can be applied to metal, glass, and plastic substrates. They produce long-lasting, slick surfaces that prevent wear and abrasion. These friction compounds are corrosion-resistant, chemically inert, and simple to maintain. Products are made to cut down on repair costs and increase element life. The coating is just a protective layer that is put to an object's surface, also known as the …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 8, Issue 3, 2021 · pp. 28–32 Read article
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Implementation of Internet Access in MPLS-VPN Technique on ISP
Abstract: Abstract: This paper proposes internet access along with MPLS VPN network to provide internet connectivity. MPLS VPN network are service provider that provide MPLS Layer 3 VPN service connectivity for customer. Usually customer request internet access from the service provider that contains access. It is possible, that in case of MPLS VPN service provider can provide internet access for customer as well. Internet access for VPN can customer can be …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 1, 2019 · pp. 25–31 Read article
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ArcGIS Map - Location Based Khasra, Village & Property Mapping with Offline Functionality
Abstract: Abstract: This project is based on real time requirement and very useful for society. As we know that in today’s time everything is going to be online. By using this project one can know about his/her own registered property details like khasra number, khasra area, landowner name, land type, property location etc. In this project we have implemented custom map of a city for user's property with some important details …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 1, 2019 · pp. 15–24 Read article
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Remote Sensing to Process for Information
Abstract: AbstractRemote sensing ever procuring sensibility acted from atmospheric windows to vary radiation waves mm ranges from thermal status to gigahertz from radio detection and ranging (RADAR). Natural electromagnetic waves have originated formation of passive sensor and artificial emissions origin active sensor. Aerial photography of civil engineering has prompting rescues from satellite imagery. Individual pixel analysis from focused regime scoped analytical methods to origin knitted full image special pattern. Evolution of …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 3, 2019 · pp. 24–30 Read article
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Design of a Stacked Aperture Coupled Microstrip Antenna for UWB Applications
Abstract: The paper presents a stacked T-shaped Aperture coupled microstrip antenna designed for ultra-wide band wireless applications. The proposed UWB antenna covers two frequency bands as of 2.49 to 2.9 GHz and 6.85 to 20 GHz and used for the various applications like Bluetooth, Zig-Bee (2.4 GHz), C band (6 to 8 GHz), X band (8 to 12 GHz), Ku band (12 to 18 GHz) and Satellite communication. The stacked antenna …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 4, Issue 1, 2017 · pp. 12–16 Read article
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Security & Privacy Challenges & Solution in IoT: A Review
Abstract: Internet of Things (IoT) is rapidly growing technology where various objects can communicate with each other and may be controlled over the internet. IoT is making life of people much easier and that's why its trend is increasing day by day. Millions of devices have already been connected through internet and more are expected to be connected in upcoming years with much faster speed. As its scope is getting bigger, …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 8, Issue 2, 2021 · pp. 7–11 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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High Gain Antenna Array (2x1 and 4x1) Design for WLAN Application
Abstract: Micro-strip antennas became very popular in 1970s primarily for space borne applications. Today they are used for government and commercial applications. These antennas consist of a metallic patch on a grounded substrate. The metallic patch can take many different configurations. However, the rectangular and circular patches are most popular because of ease of analysis and fabrication, and their attractive radiation characteristics, especially low cross-polarization radiation. In high performance aircraft, spacecraft, …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 1–8 Read article
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Implementation of DCC technique using differential amplifier based filter in 90nm CMOS technology
Abstract: Analog technique with feedback loop is applied to correct the duty cycle of any circuit without using more power. Pulse width modification is used to vary the duty cycle of clock signal. PMC cell is designed for expansion and contraction of pulse width. Differential amplifier based filter is used to detect the duty cycle of the particular clock signal. Differential amplifier and OpAmp are used to achieve adequate gain. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 13–22 Read article
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Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor
Abstract: Crosstalk is common in any digital systems and may occur due to coupling of signals which eventually have an impact on the working of a system. In this paper, an attempt is made to study the effect of crosstalk in 8-bit slice ALU, designed using 120 nm technology and suggested a method to reduce the crosstalk.Keywords: ALU, signal integrity, metal layers
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 28–32 Read article
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Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Abstract: Carry select adder is the high speed adder which is designed to speed up arithmetic operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is used …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 25–29 Read article
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A Cuckoo Search based Approach for Solving Standard Cell Placement Problem
Abstract: The standard cell placement (SCP) is an NP complete problem in VLSI layout which focuses on placing the cells at appropriate locations so as to minimize the resultant wirelength. The standard cell placement is one of the significant phases in VLSI circuit design. Many heuristic approaches have been developed in literature to solve this problem. The paper presents an efficient nature-inspired meta-heuristic algorithm for solving the standard cell placement problem …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 1–7 Read article
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Methodology of Standard Cell Library Design in .LIB Format
Abstract: The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis flows. In this paper, to best of our knowledge and information in any published literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for creating characterized timing table has been developed using 250 …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 30–38 Read article
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Design and Implementation of Low Noise Amplifier using 90 nm MOS Technology for Bluetooth
Abstract: In the era of Miniaturization it is necessary that analog field develops at par with the digital world. To design RF circuit on the single chip it is necessary that noise performance of active semiconductor devices are studied and configure the devices in such a way that noise gets minimized. In this paper various kinds of noise in the devices are explained at a brief. Low Noise Amplifier for Bluetooth …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 3, 2014 · pp. 13–19 Read article
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Switched Capacitor-based RC Filter
Abstract: Today we know that the demand of low voltage for low power integrated circuits (ICs) are used for growing the portable equipment in all the markets including telecommunication, computers and customer electronics with smaller size. The low voltage need for ICs is also motivated by the new dip submicron complementary metal oxide semiconductor (CMOS) technology scaling that required all transistors of smaller size. In current years, a lot of researches …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 32–40 Read article
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Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC
Abstract: As per emerging issues in analog-mixed signal (AMS) design towards high-speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the analog-to-digital converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 99–103 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Wire Network Survivability for Upgraded Consistency in Smart Power Grids
Abstract: Power transmission system infrastructures transmit energy over a long distance and are essential to the operation of urban society. These configurations progressively reflect highly coupled cyber-physical structures where automated telecommunications networks are used to transmit status and control details to power transmission grid elements, i.e. smart grids. However, due to the high degree of interdependence between the contact and power grid layers, malfunction incidents may contribute to more loss of …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 16–21 Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article
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Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications
Abstract: In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-shortchannel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drainextension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device isscalable up-to 10nm with a maximum On-current of …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 32–44 Read article