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808 articles for “supply”
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Digital Manufacturing Practices using 3D Printing in Indian Manufacturing Sector to Improve Productivity in Alignment with Industry 4.0
Abstract: Advancement in information technologies and intelligent production systems are being encouraged by the latest industrial revolution, known as Industry 4.0. In this new movement, additive manufacturing, or AM, is seen as a necessary component. A thorough analysis of AM technologies and their contributions to Industry 4.0 are provided in this publication. The three primary areas of AM that are the subject of this review are process development, design consideration improvements, …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 10, Issue 3, 2023 · pp. 38–47 Read article
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Sun Powered Vitality through Sun Powered Space Stations
Abstract: Traditional vitality sources will last just up to the center of the following century because of improvement in expectation for everyday comforts and hazardous populace development. Sun oriented power from space (SPS) guarantees spotless and everlasting vitality supply for the development of the humanity. With the condition of workmanship advancements yet created, SPS is attainable however not monetary. Key issues with respect to SPS are dispatch taken a toll, productivity …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 4, Issue 3, 2017 · pp. 16–21 Read article
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Finding Churn Trend Scenario Using ML Techniques
Abstract: Abstract Media transmission and in addition the network access suppliers assumes an essential part in the mobile communications and the data society. Telecom segment is consistently developing with its progression in highlights and innovation. Consumer loyalty is an imperative factor which chooses the execution of firms. Customer churn expectation is an essential technique in CRM (Customer Relationship Management), knowing the churn propensity appeared by the customers helps to take better …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 1, 2019 · pp. 1–8 Read article
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High Speed Low Offset Power Efficient Fully Differential Double Tail Dynamic Comparator
Abstract: This paper comprises a novel fully differential double tail high performance comparators suitable for low-voltage low-power applications. A fully differential double tail comparator has been designed to meet the requirement of high speed, low power consumption with low offset voltage. Authors have proposed novel architecture of dynamic voltage comparator which is differential and double tail and verified the architecture by simulation in TSMC 180nm technology with ±0.9V supply. The proposed …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 7–16 Read article
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Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article
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Comparative Analysis of High Speed Comparator for A to D Converters
Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology
Abstract: Low noise amplifier (LNA) is terribly important block in designing broadband receivers for wireless broadband communications. Being the primary active element in receiver chain it creates larger demand for LNAs that are smaller, consume less power, and provide sufficient gain, low noise and high compact design. The projected LNA is extremely integrated with low noise figure having wide calibration range with improved RF power handling system and acquires less space …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 37–44 Read article
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A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
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A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic
Abstract: Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
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Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Comparative Analysis of Low-Power Adiabatic Techniques
Abstract: In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 53–58 Read article