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794 articles for “FRL Unit”
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Optimization of Production Scheduling using Multi-Tasking by Multi-Population Genetic Algorithm
Abstract: Production scheduling is an important activity for manufacturing and engineering, where it can have a major impact on the productivity of a production system. Traditional in-house manufacturing involves production machines with dedicated operators. Here, multitasking technique is used to optimize the production scheduling problem. In parallel machine scheduling, there are n jobs and m machines and each job needs to be executed on one of the machines during a fixed …
Published in Journal of Production Research & Management · Vol. 5, Issue 1, 2015 · pp. 18–26 Read article
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Different Compressor Adders
Abstract: AbstractMultipliers are one of the main blocks which decide the circuit performance as well as computation speed. In multiplication, addition of partial products contributes most to the circuit delay, power, and area. In this project, compressor adders are used to reduce this delay. Hence, compressors are a major part of the multiplier circuit that decides the overall speed of the system. For high-speed processing and higher systems, a huge number …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 2, 2018 · pp. 19–26 Read article
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The Emerging Technologies in the Field of Semiconductors Along with the Use of the System on Chip
Abstract: An entire electronic or computer system can be combined onto a single platform using a system on chip, which is effectively an integrated circuit. The primary objectives underlying the development of this system on chip are to decrease energy waste, cut costs, and decrease the area occupied by massive systems. Students can understand and experience many methods utilised at each level of the design hierarchy using this strategy. The expansion …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 8–15 Read article
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Analysis of RC Frames Using Different Bracing Systems in Different Positions and Zones
Abstract: Structures are mainly built to enhance the performance of several activities like recreation, transportation, power generation, etc. They are built to sustain the loads coming on them during their service life by carrying adequate strength and also limit the deformation by possessing enough stiffness. Strength of a structure depends mainly upon the characteristics of material with which it is constructed. Stiffness is dependent upon the cross-sectional and geometrical properties of …
Published in Journal of Structural Engineering and Management · Vol. 3, Issue 1, 2016 · pp. 16–27 Read article
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Steel Ductile Detailing of Moment Resisting Frames for Pre-engineered Buildings
Abstract: Long span structures with no interrupting column are necessary in any type of industrial structures and pre-engineered buildings (PEB) satisfies this need along with less time and cost as compared to conventional structures. This methodology is adaptable not only due to its quality pre-designing and prefabrication, but also due to its light weight and economical construction. The concept includes the technique of providing the best possible section according to the …
Published in Journal of Structural Engineering and Management · Vol. 3, Issue 1, 2016 · pp. 36–44 Read article
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Parameteric Equation Development for Cutting Cost vs Depth of Cut for Multi Blade Granite Block Cutting Machine
Abstract: The stone processing industry has a very huge market in world. There is only three basic need of a human i.e. food, clothes and shelter, where stone covers big part of shelter, hence the requirement is also high. Basically most of the stone processing industries in India are small scale industry. The basic detail about the stone cutting machine is discussed and along with that parametric equation for relation between …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 5, Issue 1, 2018 · pp. 8–14 Read article
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Examination of the Physicochemical Properties of Lube Oil on the Effect of Load Utilization in a Generator Set
Abstract: Evaluation of the performance of lube oil in the generator on the effect of load utilization was studied to examine the effect on the quality. The continuous running of the generator set, and the load utilization reduces the quality of the lube oil which influences the operational performance. The quality of the lube oil used in servicing generator set experienced degradation with increase in operational hours as well as loss …
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 9, Issue 1, 2022 · pp. 1–9 Read article
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Ant-Optimized Scheduling for Efficient-Energy Coverage in WSNs
Abstract: AbstractIn Wireless Sensor Network, Sensors are the primary units but the nature of sensors are not inheritable and because of this limitation there is dependably an indispensable concern while in transit to use confined vitality successfully. So, Efficient-Energy Coverage (EEC) settlement is an important concern for Wireless Sensor Network (WSN). The solution of this problem is scheduling of the different activities of the devices in the network and helps to …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 3, 2018 · pp. 6–11 Read article
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A Review for Performance Improvement (BER, PAPR) of OFDM Signals by using Various Modulation Techniques & Selective Mapping Companding, Partial Transmit Sequences Companding Techniques
Abstract: The OFDM may well be a multicarrier modulation technique has proved itself at intervals the sector of high-speed communication sanctioning current technologies to attain a high transmission rate. It’s used in most communication standards. One in each of the most drawbacks of OFDM modulation is that the sturdy PAPR of the following signals. This characteristic makes OFDM signals really sensitive to the nonlinearities of analog parts, notably those of power …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 6, Issue 2, 2019 · pp. 26–33 Read article
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System
Abstract: A multimedia system links images and audio to distribute and transmit information to users. These images and audio data have to be compressed for raising capacity of storing and processing tasks in real time without losing the required information. This paper introduces an audio processing unit by using the FPGA hardware board. This is a complete Embedded system where the audio compression and decompression core is firstly described as a …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 34–44 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter
Abstract: This paper deals with design and optimization of a cascode current mirror folded cascode operational transconductance amplifier is done in order to optimize MOS transistor sizing. The design of folded cascode OTA, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18μm process, show that …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 12–23 Read article
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A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic
Abstract: Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver
Abstract: This paper deals with design and optimization of folded cascode OTA-C filter, which works for frequencies that lead to a base band circuit design for RF application, is based on transistor sizing methodology and Simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a Unit gain bandwidth of around …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 8–24 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Power Reduction at 90 nm through Circuit Level Modification
Abstract: Along with dynamic power, leakage power has turned out to be a major contributor to the overall power consumption in VLSI circuits. This problem is even more stringent in nano-scale dimension devices according to the International Technology Roadmap for Semiconductors (ITRS). As the technological advancements demand more function per device with a significant shrinking in device dimension, heat per unit area is also escalating at an elevated rate. This turns …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 101–107 Read article