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190 articles for “VLS”
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VHDL Implementation of 4 Bit Multipliers: Comparative Study with Vedic Multiplier
Abstract: The multiplier and adder are the basic building blocks of ALU of any processor and speed of this processor are greatly depends on these building blocks. The performance of multipliers can be analyzed using its performance parameters like speed, power consumption, complexity, etc. In digital signal processors as well as in general processors high speed can be achieved using this multiplier block. The Vedic multiplier architecture exhibits speed improvements and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 122–127 Read article
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Development of High Slew-Rate CMOS Operational-Amplifier
Abstract: In this paper operational-amplifier with high slew rate has been introduced. The simulation is carried out in 180 nm technologies. The supply voltage for 180 nm is 1.8 V. Different analysis for various characteristics of the operational amplifier such as gain, phase margin, slew rate, offset voltage and power dissipation is carried out in 180 nm CMOS technology. A current replicating branch with scaled-down transistors in combination with adaptive loads …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 128–131 Read article
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Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC
Abstract: Normal 0 false false false EN-IN X-NONE X-NONE As the technology is scaling, digital systems perform well with that but analog systems undergo degradation in their performance due to reduced gain. Thus, to improve their performance various calibration techniques are used. This paper implements one of such a digital calibration technique using digital signal processing, to compensate for the errors in 12-bit pipelined ADC with 1.5 bit/stage architecture at lower …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 104–113 Read article
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Implementation of Sub Parts of SAR ADC
Abstract: This paper describes the implementation of different sub parts of SAR ADC using a 180 nm CMOS technology in Mentor Graphics Tool. There are mainly four blocks in the SAR ADC. They are sample and hold, dynamic latch comparator, SAR logic and DAC logic. The simulation results show the transient analysis waveforms of different blocks of SAR ADC. Here to reduce power consumption dynamic latch comparator is used. Here the …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 139–147 Read article
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Single OTRA Based First Order Multifunction Filter
Abstract: A first order voltage mode (VM) multifunction filter has been proposed in this paper. It uses a single operational trans-resistance amplifier (OTRA) and few passive components. The same topology can be used for the implementation of first order low pass (LP), high pass (HP) and all pass (AP) filter functions. The LP and HP filters proposed here have variable gains and orthogonal tunability of gain and cut-off frequency. The theoretical …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 1–6 Read article
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Voltage Mode Second Order Multifunction Inverse Filter Using Single OTRA
Abstract: In this paper, a single operational transresistance amplifier (OTRA) based voltage mode single input single output (SISO) second order multifunction inverse filter configuration is proposed. The configuration offers an electronically tunable pole frequency and a quality factor of 1 which remains constant for any value of pole frequency. All the five inverse filters viz. inverse low-pass, inverse high-pass, inverse bandpass, inverse notch and inverse all-pass are realized from the same …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 7–12 Read article
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Effect of Doping and Crystal Orientation on Channel Current for Multigate Si Nanowire FET
Abstract: This manuscript investigates the effects on channel current by varying gate orientation as well as channel doping concentration for Si nanowire FET. Both gate and drain voltage biasing are considered here for showing variations in channel current. After analyzing simulation results for silicon 100 and 110 crystal orientation it has been found that gate all around and top gate only show significant increment in channel current on different occasions over …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 20–29 Read article
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Comparative Analysis of Various Existing NT SRAM Cells with High Speed Low Power 8T SRAM Cell
Abstract: The high speed along with low leakage devices are in demand in current CMOS technology era. With the advancement of technology, it is a big challenge to keep the balance of sizing and other parameters such as leakage current, delay and stability. In this paper, different cell topologies 6T, 7T, 8T, 9T and 10T SRAM cell are discussed and compared with the proposed single ended 8T SRAM cell. The comparison …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 30–36 Read article
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A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology
Abstract: Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 37–44 Read article
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FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals
Abstract: Filtering a signal in general involves spectrum modification by blocking or allowing the required portions of the spectrum based on the frequency requirement. Filters are designed based on the requirements for manipulating the signal for a desired application. This paper focuses on the existing architectures for developing FIR filters and also describes a new method to develop a multiplier-less filter which is suitable to implement any type of FIR filter. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–53 Read article