Journal of VLSI Design Tools and Technology
FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals
Abstract
Filtering a signal in general involves spectrum modification by blocking or allowing the required portions of the spectrum based on the frequency requirement. Filters are designed based on the requirements for manipulating the signal for a desired application. This paper focuses on the existing architectures for developing FIR filters and also describes a new method to develop a multiplier-less filter which is suitable to implement any type of FIR filter. The proposed architecture helps in area reduction and it also increases the computational speed. The proposed architecture is most suited for FPGA implementation as it does not use the conventional multiply and accumulate operations which involve the usage of more number of multipliers and adders. The proposed architecture can be used for higher frequency signals which involve a large number of filter coefficients.Keywords: FIR filter, MAC, DA based filterCite this ArticleSrividya P. FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals. Journal of VLSI Design Tools & Technology. 2017; 7(2): 45–53p.References (8)
- Paul Metzgen, Dominic Nancekievill. Multiplexer Restructuring for FPGA Implementation Cost Reduction . In Proc. IEEE Design Automation Conference. Jun 2005; 421–426p.
- Yunlong W, Shihu W, Rendong J. An Extreme Simple Method for Digital FIR Filter Design. In Proc. 3rd IEEE International Conference on Measuring Technology and Mechatronics Automation. 2011; 410–413p.
- Cui Guo -wei, Wang Feng -ying. The Implementation of FIR Low-Pass Filter Based on FPGA and DA. IEEE Intelligent Control and Information Processing . Jun 2013; 604–608p.
- Meyer-Baese U, Botella G, Romeroa D, et al. Optimization of High Speed Pipelining in FPGA -based FIR Filter Design using Genetic Algorithm. In Proc. SPIE 8401, Independent Component Analyses, Compressive Sampling, Wavelets, Neural Net, Biosystems, and Nanoengineering . May 2012.
- Meyer-Baese U. Digital Signal Processing with Field Programmable Gat e Arrays . Springer; 2007.
- Kumm M, Moller K, Zipf P. Dynamically Reconfigurable FIR Filter Archi tectures with Fast Reconfig uration. IEEE Reconfigurable and Communication - Centric Systems -on-Chip (ReCoSoC). Jul 2013; 1–8p.
- Xilinx Distributed Arithmetic FIR Filter Data Sheet. Apr 2005.
- Yajun Zhou, Pingzheng Shi. Distributed Arithmetic for FIR Filter Implementation on FPGA. In Proc. IEEE International Conference on Multimedia Technology . 2011; 272–279p. Cite this Article Srividya P. FPGA Implementation of Multiplier-less FIR Filter to Handle Higher Frequency Signals. Journal of VLSI Design Tools & Technology. 2017; 7(2): 45–53p.