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239 articles for “Thresholding”
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A Comparative Analysis of Various Flipped Voltage Follower Cells
Abstract: Flipped voltage follower (FVF) cell is used for designing low-voltage/low-power analog circuits. It can operate with a single supply voltage, less than the sum of the threshold voltages of a PMOS and NMOS transistor. The three different configurations of the FVF cell namely conventional FVF, FVF using level shifter (FVFLS) and FVF using bulk driven technique (FVFBD) are presented. Various parameters such as input/output swing, gain, bandwidth and power dissipation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 2, 2017 · pp. 1–8 Read article
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A Low Power Low Voltage High Performance CMOS Current Mirror with Improved Output Impedance
Abstract: The current mirrors are very useful in the designing of mixed mode and analog circuits. A high performance CMOS current mirror with high output impedance and a small power supply close to the threshold voltage of the transistor are presented in this paper. For achieving the high output impedance, an additional transistor is used at the output section of the current mirror. This additional transistor will improve the output impedance …
Published in Journal of Microelectronics and Solid State Devices · Vol. 3, Issue 1, 2016 · pp. 14–19 Read article
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Real-time Implementation of Binary Mask Algorithm for Hearing Prosthetics
Abstract: As the current speech enhancement algorithms can give results for improved speech audibility only. So, our main motivation is to develop speech enhancement algorithm that would improve performance in speech for hearing impaired persons. In this paper, an algorithm is presented for improving speech intelligibility. Various speech enhancement algorithms were developed but only some of them can be used for real time hearing aid applications. This proposed algorithm can be …
Published in Journal of Microelectronics and Solid State Devices · Vol. 3, Issue 1, 2016 · pp. 36–42 Read article
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Design Simulation and Assessment of Image De-noising through Improved Median Filters Based Sub band Decomposition
Abstract: The quality of an image sequence can degrade due to a number of causes, such as noise in the recording, transmission, or scanning. Additionally to enhancing the visual appeal, filtering offers the advantage of facilitating subsequent image processing tasks like coding, interpretation, or analysis. While attempting to restore a perfect image from a faulty copy, noise reduction is a top concern. Because of this, there isn't a single strategy that …
Published in Journal of Microelectronics and Solid State Devices · Vol. 9, Issue 2, 2022 · pp. 9–21 Read article
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Thermally Responsive Electroluminescence in ZnS: Mn Phosphors: Experimental Insights
Abstract: ZnS: Mn phosphors and thin film technologies have been used to create alternative current thin film light emitters. Establishing a precise model for these devices becomes challenging because they rely on frameworks that have a definitive effect on the final product, such as the size of the molecules used, the phosphor fabrication process, and the doping concentration, the purity of ZnS, the device structure, and so forth. The ZnS: Mn …
Published in Journal of Microelectronics and Solid State Devices · Vol. 10, Issue 2, 2023 · pp. 9–14 Read article
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A Comparative Analysis of Physio-Chemical Properties of Local and Imported LPG On the Ghanaian Market
Abstract: Lignified Petroleum Gas (LPG) is gaining much usage as a fuel globally including Ghana.According to the Ghana 2021 Population and Housing Census, LPG as a main source of cooking fuel increased from 18.2% in 2010 to 36.9 % in 2021. LPG in circulation is produced from three main sources. These are from Tema Oil Refinery (TOR), Ghana National Gas Company (GNGC) and from Imports (IM). However, there are been some …
Published in Journal of Petroleum Engineering & Technology · Vol. 12, Issue 3, 2022 · pp. 38–42 Read article
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Simulation Study of Process Variations in Double Gate Junctionless Field-Effect Transistors
Abstract: This work discusses the process variations in symmetrical double-gate (DG) junctionless (JL) field-effect transistors (FETs) by device simulation. Output I-V characteristics along with subthreshold slope increase, DIBL variations with drain voltage and threshold voltage shift variations are systematically analyzed with the general variability issues including oxide thickness, channel thickness and doping concentration. Potential distribution in the body channel region is also analyzed. Optimum values of the variability factors are considered …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 2, 2015 · pp. 18–27 Read article
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3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters
Abstract: Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 2, 2014 · pp. 1–8 Read article
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On a Nanocomposite Metal Oxide Thin-film Transistor with Nanofilm Gate Dielectric Material: Material Chemistry, Sol–Gel Process and Electronic Worthiness
Abstract: ABSTRACT : ILO based MOTFT is fabricated with PBZ gate dielectric. PBZ is formed over doped Si substrate by cheap sol-gel process. Thin film PBZ is analysed with XRD, UV-Vis and AFM. IZO is used as bottom gate to contact TFT. This device needs only 5V as operating voltage, and so is good for lower electronics <40V. It shows excellent e-mobility 4.5cm2/V/s, with on/off ratio 5x105 and sub-threshold swing 0.35V/decade.
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 6, Issue 3, 2019 · pp. 8–12 Read article
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FPGA Implementation of LDPC Codes
Abstract: AbstractLow Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 5, Issue 1, 2018 · pp. 21–28 Read article
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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability
Abstract: The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 35–44 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article
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Memristor Modelling for Common Source Amplifier Using 180 nm Technology
Abstract: The objective of this research paper is on memristor modeling for common source amplifier circuit using cadence virtuoso tool at gpdk 180 nm technology. A memristor is the fourth element count after resistor, inductor and capacitor in fundamental electrical circuits assumption is proposed by Leon Chua, its characteristics is based on already occurred principles of voltages (V), current (I), flux (ᵩ) and charge (q). Ohm’s law states relation voltage to …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 45–54 Read article
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Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects
Abstract: The Low power bus architecture [9, 12, 13] consists of Driver, Receiver and Interconnects in between them inside the Chip. The Low power bus architecture [1] models are classified in to Symmetric and Asymmetric [7, 11, 14, 15] based on low voltage scaling technique and very simple design principles were utilized to construct driver, receiver and interconnects. The low power bus driver has the ability to switch from a low …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 20–27 Read article
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS) > 1
Abstract: Comparator is the circuit that compares an analog signal with the reference signal and produces the binary output based on comparison. A Comparator is the main block in the ADC design as it directly affects the conversion rate of an ADC. Depending on the type and architecture of the comparator, the comparator can have significant impact on the performance of the target application. The speed and resolution of an ADC …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 47–52 Read article
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Switched Capacitor-based RC Filter
Abstract: Today we know that the demand of low voltage for low power integrated circuits (ICs) are used for growing the portable equipment in all the markets including telecommunication, computers and customer electronics with smaller size. The low voltage need for ICs is also motivated by the new dip submicron complementary metal oxide semiconductor (CMOS) technology scaling that required all transistors of smaller size. In current years, a lot of researches …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 32–40 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article