Journal of Electronic Design Technology
Volume 1, Issue 1-3 (2011)
Published
Table of contents
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Design And Implementation Of Audio Steganography On Fpga
Abstract: As the emergence of latest hacking programs and attention of hackers in hacking more and more data, the need arises to make an integrated circuit that can help hiding the message in such a form that no one can hack it easily. The audio Steganographer is a device or an integrated circuit that facilitates the user to hide a massage in the ongoing digital audio stream. It also ensures the …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 1–6 Read article
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On-Wafer Calibration of Vector Network Analyzer – Fabrication of LRM Calibration Standard
Abstract: Vector network analyzer or VNA has become ascendant of most measuring networks above 1 GHz. These networks consist of various manufacturing defects (due to resistance, capacitance and inductance) including VNA errors. To measure these errors, VNA was calibrated using a calibration kit. The usage of this calibration kit squanders a lot of time and money; moreover, the results are not accurate. To avoid this, the concept of on-wafer calibration is …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 18–25 Read article
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Performance Analysis of DG FinFET for Ultralow-power Subthreshold Applications
Abstract: Subthreshold operating region of transistor shows huge potential toward satisfying demand of ultralow power (ULP) consumption from handheld portable devices. However, operating device with such small subthreshold leakage current as a switching current gives huge penalty in their operating frequency. For subthreshold operating region key design goal is to boost the speed of the device. DG FinFET device shows excellent device characteristics in subthreshold operating region. In this paper, 1-bit …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 26–33 Read article
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Virtual Fabrication and Analog Performance of Sub-40nm Bulk MOSFET
Abstract: Virtual Fabrication of sub-40nm Bulk MOSFET is carried out under channel engineering and source drain engineering process. These structures enable more aggressive device scaling in nano-scale region because of their ability to control short channel effects. How ever during scaling the junction depth should also be scaled down, which increases parasitic resistance so silicidation technique has been applied to reduce their effects on device. Analog performance has been measured in …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 34–40 Read article
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Design and Optimization of Nano scale Double Gate SOI-MOSFET for Analog Applications Using SILVACO TCAD
Abstract: In this paper the structure effect on electrical characteristics of 60-nm double-gate Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor (DG-SOI-MOSFETs) is explored. These structures enable more aggressive device scaling in nano scale region because of their ability to control short channel effects. Established a scaling theory which gives guidance for the device optimization (Silicon film thickness Tsi (20nm); gate oxide thickness Tox (3nm); buried oxide thickness Tbox (200nm) and gate length LG …
Published in Journal of Electronic Design Technology · Vol. 1, Issue 1-3, 2011 · pp. 7–17 Read article