VLSI systems
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Hybrid Quantum-Classical Reinforcement Learning Enabled Thermal-Aware Electronic Design Automation Framework for Energy-Efficient Next-Generation VLSI Systems Applications
Abstract: Modern Very Large-Scale Integration (VLSI) systems are becoming more complicated, which has increased need for sophisticated Electronic Design Automation (EDA) frameworks that can concurrently optimise thermal behaviour, power consumption, and performance. This study proposes a Hybrid Quantum-Classical Reinforcement Learning (HQCRL) Enabled Thermal-Aware EDA Framework for next-generation energy- efficient VLSI systems. The proposed framework integrates quantum-inspired optimization techniques with classical reinforcement learning algorithms to address the challenges of placement, routing, and …
Published in Journal of Electronic Design Technology · Vol. 17, Issue 2, 2026 Read article
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Deep Learning-Based Thermal Prediction Models for Solid-State Electronic Devices
Abstract: The rapid advancement of solid-state electronic devices in high-performance computing, communication systems, automotive electronics, and renewable energy applications has significantly increased concerns related to thermal management and device reliability. Excessive heat generation in semiconductor devices adversely affects operational efficiency, switching performance, lifespan, and overall system stability. Traditional thermal prediction methods often require complex numerical computations and extensive simulation time, making them less suitable for real-time monitoring and adaptive control applications. …
Published in International Journal of Solid State Innovations & Research · Vol. 4, Issue 1, 2026 Read article
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Hardware Synchronization for Embedded Multi-core Processors
Abstract: The focus is not on whether multi-core systems are becoming prevalent, but on how microcontroller architectures should be designed to comply with stringent field requirements. This paper illustrates the transition from single to multiple cores, ensuring coherence and consistency in shared memory through hardware mechanisms. Hardware barriers are implemented to allow for point-to-point synchronization between processor cores. Practical experiments center on the initial stages of transforming single-core systems into dual-core …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 33–42 Read article