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• Published Subscription Original Research 9 Jan 2025

  RTL to GDSII Implementation UART using Verilog and Cadence tools

  By Dhruv Lalpurwala, Vandan Parekh, Robinson Paul

  Abstract: The paper outlines a thorough design flow for Universal Asynchronous Receiver and Transmitter (UART) utilizing Register Transfer Level (RTL) to Graphic Data System II (GDS II) Implementation using Verilog and Cadence tools. The process involves RTL design, logic synthesis with Genus and physical design using Innovus, followed by verification steps including formal verification, static timing analysis and power optimization. The results demonstrate an efficient workflow, highlighting the effectiveness of Cadence’s …

  Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 1–7 Read article →