Sub-7nm VLSI Design

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• Published Subscription Review Article 15 May 2026

  Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design

  By Rosalin Pradhan, Bibhu Prasad Ganthia

  Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →