PPA Optimization

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• Published Subscription Review Article 22 Aug 2026

  Implementation of a 4-Bit Synchronous Counter in SkyWater 130 nm CMOS Technology Using Open-Source EDA Tools

  By Maitra Shah, Mitesh Limachia, Narendra Chauhan, Sagar Kavaiya, Purvang Dalal

  Abstract: As semiconductor technology continues to scale down, the physical layout of integrated circuits has become increasingly critical in determining performance, power consumption, and area efficiency. This paper presents the complete physical design implementation of a 4-bit counter, from Register Transfer Level (RTL) to GDSII, using the SkyWater 130 nm open-source Process Design Kit (PDK) and the OpenLane automated physical design flow. Functional verification of the RTL design was initially performed …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 2, 2026 Read article →