High speed D-FF
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A Novel High Speed CMOS Flip-Flop Design in 16 nm Technology
Abstract: Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption as compared to the other CMOS design styles. This paper proposes a novel high speed flip flop design in 16 nm technology. The design was compared with the existing low power techniques in terms of power, and delay (clk-Q and D-Q). The proposed design was found to be 20% fast as compared to basic 9T …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 37–44 Read article