delay calculation
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Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article