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4 articles for “slew rate”
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Edge-detecting Technique to Increase Slew Rate for Differential Amplifier
Abstract: This paper addresses a very compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. With enhanced slew rate, Edge-Detecting technique the proposed buffer achieves high-speed driving performance, draws a small quiescent current during static operation. The proposed SRE design is achieved more than 68 times improvements in the slew rate without significant increase of static power dissipation. Post-layout simulations show that the proposed buffer can drive a …
Published in Journal of Electronic Design Technology · Vol. 3, Issue 1-3, 2012 · pp. 49–58 Read article
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A simulation based study of Capacitor-less Low-Dropout Regulator (LDO)
Abstract: Low-dropout (LDO) regulators have become an essential part of IC design for managing power consumption, this used large capacitors which increases the pin count and also occupies more space in chip. As the order of electronics items increses the the demand of LDO also increases.This is used used with switching regulators to defeat the value of noise and various unwanted signals and provided a low noise output In this work …
Published in Journal of Microelectronics and Solid State Devices · Vol. 8, Issue 3, 2021 · pp. 11–15 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Performance Analysis of Complimentary Pass Transistor Logic Based Multiplexer Using Dual-gate FinFET Technology
Abstract: AbstractThis paper presents the design and analysis of double gate FinFET complimentary pass transistor logic (CPL) multiplexer. The circuit of multiplexer (MUX) using CPL is used for comparison of performance parameters like average power consumption, rise/fall time, delay, slew rate, PDP and EDP. Multiplexer is a digital circuit, it has inputs and select line; select lines are used for select input lines to transfer data to the output end. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 41–48 Read article