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1 article for “power EDAC”

• Published Subscription Original Research 9 Apr 2025

  DFT Compatible Low Power EDAC Based on Clock Gating

  By Hemapriya C, Sananda S, Sneha M., Suryakala S

  Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article →