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5 articles for “parasitic capacitance”
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Thermo-Parasitic-Aware Adaptive Switching Model (TPASM) for High-Frequency Microelectronic Power Devices
Abstract: The increasing switching frequency of modern solid-state semiconductor devices has intensified the influence of parasitic inductance, parasitic capacitance, temperature-dependent conduction losses, and transient voltage and current stresses. Conventional switching-loss models generally treat these effects independently, resulting in limited accuracy when the device operates under high-frequency and thermally varying conditions. This paper proposes a Thermo-Parasitic-Aware Adaptive Switching Model (TPASM) for coupled electrical, thermal, and parasitic analysis of high-frequency solid-state devices. The …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article
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Bandwidth Enhancement of MPA using DGS
Abstract: In this paper, the authors proposed an MPA with DGS to enhance its parameters and mainly bandwidth of the antenna. To achieve a very important bandwidth enhancement the authors proposed a rectangular shaped symmetrical DGS in the ground plane. This DGS on the ground plane increases the fringing field which reluctantly increases the parasitic capacitance. This increases the coupling between patch and ground which make the bandwidth to increase from …
Published in Journal of Microwave Engineering and Technologies · Vol. 3, Issue 1, 2016 · pp. 6–10 Read article
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Signal Integrity Analysis of Single Walled Carbon Nano Tube based Interconnects at 32 nm Technology Node
Abstract: The rising demands for ultra-high-speed processors and portable devices have made the transistor and interconnect scaling a challenging issue in present days. In this work, the impedance parameter of copper and CNT based interconnects are calculated at 32 nm technology node for different lengths. The performances of CNT based interconnects are analyzed and compared with Cu based interconnects in terms of crosstalk. The conventional copper interconnects are not able to …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 33–42 Read article
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Scrutinizing and Extract the cause of Scaling Concerns for Fin-FET
Abstract: AbstractRecent Trend in the adaption of New Technological Innovations suggests that People are looking for Power in compactly sized alternatives which suggest that Devices are shrinking down day by day. With increasing demands of Power to Body ratio, it is becoming difficult for the Researchers to cope up with this current scenario. Fin-FET seems to be a possible alternative to combat these expectations but with every new invention comes its …
Published in Journal of Communication Engineering & Systems · Vol. 9, Issue 3, 2019 · pp. 8–11 Read article
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Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing
Abstract: With logical effort minimum delay of the path can be estimated by only knowing number of stages, path effort, and parasitic delay without the need to assign transistor sizes. This is superior to simulation where delay depends on sizes and you never achieve certainty that the size selected would offer minimum delay. In this work 3 cascaded inverters is being sized in the ratio 1:2:3 to achieve minimum propagation delay …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 29–31 Read article