Search results for “output resistance and intrinsic gain.”

Published Subscription 13 Jul 2021

Improvements in Analog Performance of Dual Metal Gate based Silicon-on-Insulator Junctionless Transistor with Pocket Doped Window

By Priyansh Tripathi, Narendra Yadava, Mangal Deep Gupta, R. K. Chauhan

Abstract: This paper elucidates the impact of pocket doped window on the analog performance of dual metal gate based silicon-on-insulator junctionless transistor (DMG SOIJLT). The analog parameters of proposed SOIJLT is compared with DMG based conventional SOIJLT. The findings of analog performance comparison reveal that transconductance (gm), transconductance generation factor (TGF), output conductance (gd), output resistance (r0), intrinsic gain (AV), and cut-off frequency (fT) have improved for DMG PD-SOIJLT as compared …

Published in Journal of Microelectronics and Solid State Devices · Vol. 8, Issue 1, 2021 · pp. 1–8 Read article

Published Ahead of print Open access Article 20 May 2023

Improvements in Analog Performance of Dual Metal Gate based Silicon-on-Insulator Junctionless Transistor with Pocket Doped Window

By Priyansh Tripathi, Narendra Yadava, Mangal Deep Gupta, R.K. Chauhan

Abstract: This paper elucidates the impact of the pocket doped window on the analog performance of dual metal gate based silicon-on-insulator junctionless transistor (DMG SOIJLT). The analog parameters of the proposed SOIJLT are compared with DMG based conventional SOIJLT. The findings of analog performance comparison reveal that transconductance (gm), transconductance generation factor (TGF), output conductance (gd), output resistance (r0), intrinsic gain (AV), and cut-off frequency (fT) have improved for DMG PD-SOIJLT …

Published in Journal of Microelectronics and Solid State Devices Read article

Published Subscription 15 Feb 2019

Characterization of High Performance Third Generation Current Conveyor using CMOS Technology

By Megha M. Patel, Nilesh D. Patel

Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …

Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article