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2 articles for “buried oxide (BOX)”

• Published Subscription 10 Apr 2019

  Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation

  By P. Sasikala, Priscilla Scarlet, K. K. Nagarajan, R. Srinivasan

  Abstract: In this paper, the impact of spacer engineering on 10 nm gate length planar SOI (Silicon On Insulator) junctionless transistor performance is studied using Sentaurus TCAD simulator. Spacer length and spacer permittivity of the device are taken as two controllable parameters. DC performance metrics, ION, IOFF, ION/IOFF ratio, unity gain frequency (fT) and non quasi static delay (NQS) are investigated for various spacer lengths and spacer permittivity. The simulation results …

  Published in Journal of Materials & Metallurgical Engineering · Vol. 6, Issue 2, 2016 · pp. 42–52 Read article →

• Published Subscription 9 Aug 2019

  Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era

  By manan sheth, shivang bakliwal, shival trivedi, dhaval shah

  Abstract: The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate. Keywords: Silicon on insulator (SOI), short channel effect (SCE) [2], buried oxide (BOX)

  Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 52–58 Read article →