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2 articles for “UVM Register Layer”
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Implementation of Register Access Methods for Device Configuration Using UVM
Abstract: Verification of hardware registers conjointly with their monitoring forms a huge part of any verification project. Verification using universal verification methodology (UVM) register layer enables reusability, which consequently eliminates the dependency of register layer on protocol thereby saving time by evading efforts of rewriting register sequences once the protocol changes. This paper constructs the advanced high performance bus (AHB) register verification environment to ease design configuration, thereby promoting reusability and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 132–138 Read article
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Automated Access Backdoor for UVM_REG Layer
Abstract: Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 49–53 Read article