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6 articles for “UVM”
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Implementation of Register Access Methods for Device Configuration Using UVM
Abstract: Verification of hardware registers conjointly with their monitoring forms a huge part of any verification project. Verification using universal verification methodology (UVM) register layer enables reusability, which consequently eliminates the dependency of register layer on protocol thereby saving time by evading efforts of rewriting register sequences once the protocol changes. This paper constructs the advanced high performance bus (AHB) register verification environment to ease design configuration, thereby promoting reusability and …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 132–138 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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Automated Access Backdoor for UVM_REG Layer
Abstract: Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 49–53 Read article
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Coverage Driven Verification of Synchronous FIFO using UVM
Abstract: FIFO (first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether …
Published in Recent Trends in Electronics Communication Systems · Vol. 8, Issue 4, 2021 · pp. 1–7 Read article
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Coverage Driven Verification of Synchronous FIFO Using UVM
Abstract: FIFO(first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write. Where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether there …
Published in Recent Trends in Electronics Communication Systems · Vol. 8, Issue 1, 2021 · pp. 1–7 Read article
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Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT
Abstract: Verification of a design is as important as the design itself to make it work in a practical scenario. Verification phase is an important phase in System on Chip (SoC) design cycle and used to take 70% to 80% of the total design time. A verification environment may be prepared simply using a Hardware Verification Language (HVL) only without using any methodology or using a HVL with verification methodology. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 114–121 Read article