Coverage Driven Verification of Synchronous FIFO Using UVM

C. Anusha Bhanu; Rajesh Odela; G. R. Padmini

Abstract

FIFO(first in first out) is a memory array in which the data written first into the memory will be read first with the help of the control signals read and write. Where the control signal write is used to write the data into the memory and the control signal read is used to read the data from the memory. To avoid the memory overflow and to know that whether there is a space in memory to write a few status signals are asserted, which are empty and full. The empty signal is high which means that all the memory location is the FIFO is empty i.e. no data written into it and the full signal is high then all the memory location in the FIFO occupied with some data. The FIFO has been designed with a depth of 64 locations and the size of each location is 16-bit and verify it with the help of System Verilog based UVM(i.e universal verification methodology).Coverage driven verification is being used to verify the design functional accuracy. Constrained randomization has been used to attain the maximum amount of coverage (i.e both code coverage and functional coverage). Code coverage of 99.43% and functional coverage of 100% has been achieved.

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