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1 article for “Transaction Level Modelling (TLM)”

• Published Subscription 5 Nov 2015

  Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT

  By Rakhi Nangia

  Abstract: Verification of a design is as important as the design itself to make it work in a practical scenario. Verification phase is an important phase in System on Chip (SoC) design cycle and used to take 70% to 80% of the total design time. A verification environment may be prepared simply using a Hardware Verification Language (HVL) only without using any methodology or using a HVL with verification methodology. The …

  Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 114–121 Read article →