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2 articles for “Testbench”
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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Roles and Responsibilities of Verification Language, Verification Methodology and Verification Tool for Design Verification of a DUT
Abstract: Verification of a design is as important as the design itself to make it work in a practical scenario. Verification phase is an important phase in System on Chip (SoC) design cycle and used to take 70% to 80% of the total design time. A verification environment may be prepared simply using a Hardware Verification Language (HVL) only without using any methodology or using a HVL with verification methodology. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 114–121 Read article