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1 article for “Row by Row ADC”

• Published Subscription Original Research 28 Jan 2025

  Implementation of STATIC-RANDOM-ACCESS-MEMORY-Based In-Memory Computing-architecture for improving Energy Efficiency

  By Kiran Sharma, Jitendra Ahir, Laxmi Singh

  Abstract: The in-memory-computing architecture the improvement of big data and high-performance computing. In memory-computing (IMC) as reduces the latency and power consumption of data processing. Proposed research paper static random-access memory-based IMC architecture. By completing internal write-back, NMOS transistors increase computational efficiency and eliminate the need to read the computational output right away. A 128×128 STATIC-RANDOM-ACCESS-MEMORY-IMC macro chip is designed using the 78-nm technology. The energy efficiency of 55.3TOPS/W with supply …

  Published in Journal of VLSI Design Tools and Technology · Vol. 15, Issue 1, 2025 · pp. 25–35 Read article →