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7 articles for “Reduced instruction set computer”
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Coarse-grained Logic Interface with Floating-point Arithmetic Unit: A Review
Abstract: One of the key elements of their design, which has a substantial impact, is their choice of programmable connectivity and logic capabilities. The FPGA architecture has a significant impact on the speed performance, space efficiency, and power consumption of the finished device. This examination examines the evolution of programmable logic devices over time, the underlying programming paradigms that underpin programmability, and the most important findings from architectural system research. We …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 11, Issue 2, 2023 · pp. 18–24 Read article
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Universal Microcontroller Trainer Board Design for Speed Controlling of BLDC Motor and Text Controlling of Dot-Matrix Display
Abstract: Reduce Instruction Set Computing (RISC) related micro-controlling is taking over modern life little by little. Practicing these phenomena becoming necessary in engineering sectors. In this research, a segmented laboratory-kit has been developed to involve students in controlling Brushless Direct Current (BLDC) Motor and Light Emitting Diode (LED) Dot Matrix Display. This lab kit introduces several features for those two modules. The Rotation Per Minute (RPM) measurement using Infrared (IR) sensor, …
Published in Journal of Microcontroller Engineering and Applications · Vol. 8, Issue 3, 2021 · pp. 6–21 Read article
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Architectural Evolution of RISC Processors: From Early Research Prototypes to Modern Industrial Implementations
Abstract: This paper surveys the architectural evolution of Reduced Instruction Set Computer (RISC) architectures from early research prototypes to modern industrial processors, tracing four decades of design refinement across academic, embedded, server, mobile, and open- hardware ecosystems. Core ISA principles, pipeline evolution, compiler–hardware co-design, and quantitative performance modeling are analyzed through four representative industrial implementations: MIPS 74K, SPARC T4, ARM Cortex-A72, and SiFive U74 (RISC-V). Each processor is examined in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 · pp. 29–39 Read article
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Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression
Abstract: Flexible and scalable motion estimation processor for the h.264 advanced video coding standard handling the processing requirements for high-definition video and suitable for Field-Programmable Gate Array (FPGA) implementation. The new motion estimation algorithm of kalman filter used to reduce the computational complexity. The eight custom instruction sets are used in the motion estimation. All processor instances are remaining binary compatible so recompilation process is not required. The motion estimation algorithm …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 1–5 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 45–50 Read article
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High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography
Abstract: In this paper we will study high speed energy efficient FPGA implementation using redundant sign digit elliptic curve cryptography. In existing system to design processor with high area and low speed computation process so that we proposed to low area with high speed computation using Elliptical cryptography processor. Here we use redundant signed digit to reduce the overhead due to computations. For modular arithmetic operation for multiplication, we used Karatsuba-Ofman …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 45–50 Read article
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Understanding Sentiment Trends Through Zero-Shot and Few-Shot Learning Models
Abstract: The requirement for large, manually labeled datasets is one of the main barriers to applying sentiment analysis algorithms in specialized or rapidly evolving disciplines in the present natural language processing (NLP) landscape. This work investigates a paradigm shift from traditional fully supervised learning to data-efficient methods, specifically zero-shot learning (ZSL) and few-shot learning (FSL). This study uses the advanced capabilities of instruction-tuned large language models (LLMs), like GPT-4, to assess …
Published in International Journal of Computer Science Languages · Vol. 4, Issue 1, 2026 · pp. 01–08 Read article