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2 articles for “Pipelined ADC”
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Implementation of LMS Calibration Algorithm for 12-Bit Pipelined ADC
Abstract: Normal 0 false false false EN-IN X-NONE X-NONE As the technology is scaling, digital systems perform well with that but analog systems undergo degradation in their performance due to reduced gain. Thus, to improve their performance various calibration techniques are used. This paper implements one of such a digital calibration technique using digital signal processing, to compensate for the errors in 12-bit pipelined ADC with 1.5 bit/stage architecture at lower …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 104–113 Read article
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Design of 8 Bit High Speed Pipelined ADC
Abstract: High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in many electronic applications. The demand for high-speed, medium resolution, low power ADCs is satisfied by various ADC architectures like folding, flsubranging, pipeline etc. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems. Pipelined ADC offer attractive combination of high-speed, high-accuracy and low power consumption, which …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 71–80 Read article